1. Field of the Invention
The invention relates generally to methods for fabricating FIN-FET devices. More particularly, the invention relates to methods for fabricating FIN-FET devices with enhanced performance.
2. Description of the Related Art
Field effect transistor devices are common elements within semiconductor products. They are typically formed within a semiconductor substrate. They include a gate electrode separated from the semiconductor substrate by a gate dielectric layer. A channel region of the semiconductor substrate is defined beneath the gate electrode. The channel region separates a pair of source/drain regions.
As semiconductor device dimensions have decreased, it has become more difficult to fabricate field effect transistor devices with enhanced performance. The difficulties derive from channel effects that in turn result from forming gate electrodes with reduced linewidths within semiconductor products. These channel effects are also known as short channel effects.
In an effort to minimize short channel effects within semiconductor products, the design and fabrication of FIN-FET devices has evolved. In contrast with conventional field effect transistor devices, FIN-FET devices employ an insulator substrate or an insulator substrate layer that may in turn be formed upon a semiconductor substrate. In turn, a patterned silicon fin layer is formed upon the insulator substrate or insulator substrate layer. The patterned silicon fin layer terminates in a pair of source/drain regions formed at opposite ends of the fin. A three-dimensional channel region of the fin spans between the source and drain regions. Next, a gate dielectric layer is formed upon the three-dimensional channel region. In turn a polysilicon layer is formed and patterned as a gate electrode layer that perpendicularly traverses the fin at the three dimensional channel region. Thus, the FIN-FET device has a three-dimensional gate electrode in turn formed upon a three-dimensional fin channel.
Although FIN-FET devices address many short channel effect problems of conventional field effect transistor devices, they are nonetheless not entirely without problems.
In particular, FIN-FET devices suffer from photolithographic resolution difficulties in their fabrication since they provide for forming one three dimensional layer (i.e., a gate electrode layer) upon another three-dimensional layer (i.e., a polysilicon fin layer). The difficulties become particularly pronounced since the patterned silicon fin layer is often formed of enhanced step height such as to maximize channel width properties within a FIN-FET device. It is thus desirable to provide methods for forming FIN-FET devices with enhanced resolution. The present invention is directed towards the foregoing object.